The present disclosure relates to a solid state imaging device including a pixel array unit that has a plurality of 2-dimensionally arranged pixels in a matrix and a plurality of signal lines arranged along a column direction, and an A/D (analog/digital) conversion unit is provided corresponding to each signal line and converts an analog signal output from the pixel through the signal line into a digital signal, a method of controlling the solid state imaging device, and a program for controlling the solid state imaging device.
A pixel adding method in a solid state imaging device is known as an FD adding method of summing and outputting charges of pixels on a floating diffusion (hereinafter, referred to as FD) of the pixel, a source follower adding method of simultaneously reading a plurality of pixel signals through reading lines and adding the pixel signals using a load MOS circuit connected to the reading signal lines, a counter adding method of performing digital addition using a counter circuit in a column ADC circuit, and a capacity adding method of connecting a plurality of capacitors to input ends of a comparator in a column ADC circuit in parallel and adding signals of a plurality of vertical signal lines.
The pixel addition in decimation reading of Bayer arrangement will be described with reference to FIG. 29 to FIG. 31B. FIG. 29 is a diagram illustrating an example of pixel addition performed using a column ADC circuit when the Bayer arrangement is used as a color filter array, FIG. 30 is a timing chart at the time of the pixel addition in the column ADC circuit shown in FIG. 29, and FIG. 31A and FIG. 31B are reading images when the column ADC circuit shown in FIG. 29 is used.
In the Bayer arrangement shown in FIG. 29, G color filters used as main components of brightness signals are disposed at an interval of one pixel in a checkerboard shape, R and B color filters are arranged at the remaining pixels at a pitch of vertical and horizontal one pixel in a checkerboard shape, and the R and B color filters are disposed to obliquely deviate by one pixel. The pixel array shown in FIG. 29 is configured by a pixel unit (hereinafter, referred to as an FD sharing pixel unit) that shares the FD by connection of four pixels of vertical and horizontal 2×2 through a floating diffusion (hereinafter, referred to as FD).
In the configuration shown in FIG. 29, addition and addition averaging are performed, for example, as R1 and R2, G1 and G3, G2 and G4, B1 and B2, R3 and R4, G5 and G7, G6 and G8, and B3 and B4, the same vertical signal line is shared, the same color of pixels are sequentially input to the column ADC circuit in the vertical direction, are A/D converted using the column ADC circuit of each column, and then the addition and the addition averaging is performed by a counter (for example, see Japanese Unexamined Patent Application Publication No. 2006-033454).
For example, as shown in FIG. 30, first, the pixel R1 and the pixel R3 are selected, the pixel signal of the pixel R1 is output to a vertical signal line VSL1, and the pixel signal of the pixel R3 is output to a vertical signal line VSL2. Then, the pixel R2 and the pixel R4 are selected, the pixel signal of the pixel R2 is output to the vertical signal line VSL1, and the pixel signal of the pixel R4 is output to the vertical signal line VSL2.
That is, the pixel signals of pixels R1 and R2 are sequentially output to the vertical signal line VSL1, and the pixel signals of pixels R3 and R4 are sequentially output to the vertical signal line VSL2. Accordingly, both pixel signals of the pixels R1 and R2 are counted by a counter CNT1, and both pixel signals of the pixels R3 and R4 are counted by a counter CNT2.
Similarly, the remaining pixels are sequentially selected and output to the vertical signal lines, and digital data subjected to counter addition by the counters are output.
FIG. 31A is a reading image in a state of addition in the column ADC circuit, and an image output from the column ADC circuit corresponds to a state where the number of pixels in the vertical direction is decimated by half.
Thereafter, the A/D conversion value of the pixel output from the column ADC circuit is transmitted to a logic signal processing circuit at the latter stage, and the addition and the addition averaging are performed therein in the horizontal direction. FIG. 31B is a reading image in a state of addition in the logic signal processing circuit, an image output from the logic signal circuit corresponds to a state where the number of pixels in both vertical and horizontal directions is decimated by half.
Recently, in a solid state imaging device, white as a main component of a brightness signal may be used in color arrangement of a color filter array (for example, see Japanese Unexamined Patent Application Publication No. 2010-136226).
FIG. 32 is an example of color arrangement of a color filter array including white. In the color arrangement shown in FIG. 32, white filters are disposed at a pitch of one pixel in a checkerboard shape, and RGB color filters are uniformly disposed at the remaining pixels. More specifically, the R and B color filters are arranged in checkerboard shape at a pitch of two pixels horizontally and vertically, the R and B color filters are disposed to obliquely deviate by one pixel, and the remaining pixels are the G color filters. In this case, the G filters are arranged in an oblique stripe shape.
In such color arrangement, it is difficult to perform the addition and the addition averaging using the column ADC circuit. Accordingly, the A/D conversion value of the pixel output from the column ADC circuit is transmitted to the logic signal processing circuit at the latter stage, the vertical direction addition and addition averaging and the horizontal direction addition and addition averaging are performed therein by a calculation process.
When the process of decimation of the addition and the addition averaging in the logic signal processing circuit is performed while using the color arrangement shown in FIG. 29, all sixteen pixels in the 4×4 pixel arrangement are selected, and the AD conversion is performed using the column ADC circuit provided corresponding to each vertical signal line to perform the addition and the addition averaging. That is, also at the time of the decimation outputting, it is necessary to operate all the ADC circuits, and power consumption in the column ADC circuits is not reduced.
It is necessary to transmit the addition and the addition averaging value obtained by the AD conversion to the logic signal processing unit at the latter stage and to perform the addition and the addition averaging in the horizontal direction. Accordingly, the logic signal processing unit at the latter stage has to be provided with a circuit for processing the received value or a line memory, which causes an increase of any of a circuit scale, an operation speed, and power consumption. Of course, these demerits in the logic signal processing unit are the same even in the case of the color arrangement of the filter array including the white shown in FIG. 32 described above.
In the FD addition method, and the source follower adding method, the counter adding method, and the capacity adding method in the related art described above, when the color arrangement shown in FIG. 32 is employed, it is physically difficult to perform the decimation outputting using the addition and the addition averaging in the pixels connected to the other vertical signal lines. In the case of the capacity adding method, it is possible to perform the decimation outputting using the addition and the addition averaging in the pixels connected to the adjacent vertical signal lines, but it may not be performed instead of the output method in which the decimation is not performed.